A pipeline ADC (analog-digital converter) comprises a plurality of conversion stages, including at least a first stage and a last stage. Except the last stage, each conversion stage has a succeeding stage. Except the first stage, each conversion stage has a preceding stage. Each conversion stage, except the last stage, performs the following functions: receiving an analog input signal; performing a coarse analog-to-digital conversion on the analog input signal to generate an intermediate digital code; generating a residual signal that represents the difference between the analog input signal and a signal level corresponding to the intermediate digital code; amplifying the residual signal by a inter-stage gain factor to generates an analog output signal, which is passed to a succeeding stage as the analog input signal for the succeeding stage; receiving a digital input code from its succeeding stage; and combining the digital input code with the intermediate digital code into a digital output code, which is passed to its preceding stage (if applicable) as the digital input code for the preceding stage. The last stage receives an analog input signal from its preceding stage and performs a coarse analog-to-digital conversion on the analog input signal to generate a digital output code, which is passed to its preceding stage as the digital input code for the preceding stage. For each conversion stage except the last stage, the digital input code received from its succeeding stage presents a result of an analog-to-digital conversion on the analog output signal that it passes to its succeeding stage. Note that when generating the analog output signal, amplification of an inter-stage gain factor has been introduced so as to efficiently utilize the dynamic range of the succeeding stage. Therefore, when combining the digital input code with the intermediate digital code to generate the digital output code, the inter-stage gain factor that is involved in generating the analog output signal and passing it to the succeeding stage needs to be taken into account. For instance, a conversion stage that performs a 1-bit analog-to-digital conversion has a nominal inter-stage gain factor of two. So, when combining the digital input code with the intermediate digital code into the digital output code, the intermediate digital code needs to be scaled by a factor of two, or alternatively the digital input code needs to be scaled by a factor of one half, to account for the effect of the inter-stage gain. If somehow the actual inter-stage gain factor deviates from the nominal inter-stage gain factor, an error occurs due to the mismatch between the actual inter-stage gain factor used in the amplification and the assumed inter-stage gain factor used in combining the digital input code with the intermediate digital code. In many pipeline ADCs, the deviation from the nominal inter-stage gain factor is a major source of error. What is needed is an efficient method for correcting the error due to the deviation from the assumed inter-stage gain factor.